1. Field of the Invention
The invention relates to an analog/digital converter (hereinafter, referred to as xe2x80x9cADCxe2x80x9d) for converting an analog voltage into a digital signal and, more particularly, to a technique for preventing errors which are caused due to external noises of a dual-slope conversion type ADC.
2. Related Background Art
FIG. 2 is a constructional diagram of a conventional dual-slope conversion type ADC.
The dual-slope conversion type ADC has an analog switch 1 for switching an input voltage Vi as a conversion target and a reference voltagexe2x88x92Vr and inputting the switched voltage. An operational amplifier 2 constructing a voltage follower is connected to an output side of the analog switch 1. An output side of the operational amplifier 2 is connected to an inversion input terminal of an operational amplifier 4 through a resistor 3. A capacitor 5 and an analog switch 6 are connected in parallel between the inversion input terminal of the operational amplifier 4 and its output terminal. A non-inversion input terminal of the operational amplifier 4 is connected to a base voltage GND. The output side of the operational amplifier 4 is connected to a first input terminal of a voltage comparator 7. A second input terminal of the voltage comparator 7 is connected to the base voltage GND and its output side is connected to a control circuit 8.
The control circuit 8 generates control signals C1 and C6 to the analog switches 1 and 6 and generates a control signal C9 to a counter 9 on the basis of an output signal S7 of the, voltage comparator 7. The counter 9 counts the number of clock signals (not shown) in response to the control signal C9. A count value of the counter 9 is outputted as a digital signal OUT corresponding to the input voltage Vi.
FIG. 3 is a signal waveform diagram showing the operation of the circuit shown in FIG. 2. In FIG. 3, a solid line indicates an integration voltage V4 on the output side of the operational amplifier 4 in the case where the input voltage Vi is large, and a broken line shows the integration voltage V4 in the case where the input voltage Vi is small.
First, for a reset period from time 0 to time T0, the analog switch 6 is short-circuited by the control signal C6 which is generated from the control circuit 8 and the capacitor 5 is discharged. Since the non-inversion input terminal of the operational amplifier 4 is connected to the base voltage GND, an electric potential at the inversion input terminal is also set to the base voltage GND and the integration voltage V4 is set to the base voltage GND (that is, 0V).
Subsequently, at time T0, the analog switch 6 is opened by the control signal C6. and the input voltage Vi side of the analog switch 1 is selected :by the control signal C1. Thus, a current which is supplied from the output side of the operational amplifier 2 to the resistor 3 is set to Vi/R (where, R is a resistance value of the resistor 3).
In the ideal operational amplifier 4, since the electric potential at the inversion input terminal is equal to the base voltage GND and an input impedance is infinite, the whole current flowing in the resistor 3 is charged into the capacitor 5. Thus, the integration voltage V4 after the elapse of a predetermined time t1 of the first integration period is equal to xe2x88x92(1/CR)Vixc2x7t1 (where, C is a capacitance of the capacitor 5).
A second integration period is started at time T1 after the elapse of time t1 from time T0. The control signal C9 to start the counting operation is generated from the control circuit 8 to the counter 9 and the analog switch 1 is switched to the reference voltage xe2x88x92Vr side by the control signal C1. Therefore, a current of xe2x88x92Vr/R is supplied from the output side of the operational amplifier 2 to the resistor 3.
The integration voltage V4 after the elapse of time t2 from time T1 is expressed by the following equation (1).
V4=xe2x88x92(1/CR)Vixc2x7t1+(1/CR)Vrxc2x7t2xe2x80x83xe2x80x83(1)
When the integration voltage V4 is equal to the base voltage GND, the signal S7 is generated from the voltage comparator 7 to the control circuit 8. The control circuit 8 stops the control signal C9, thereby stopping the counting operation of the counter 9. From the equation (1), time t2 is expressed by the following equation (2).
t2=(Vi/Vr)t1xe2x80x83xe2x80x83(2)
Since Vr and t1 are set to predetermined values, time t2 is proportional to the input voltage Vi and the digital signal OUT which is outputted from the counter 9 is equal to a value that is proportional to the input voltage Vi.
However, the conventional dual-slope conversion type ADC has the following problem.
When noises are inputted from the outside during the converting operation, the voltage that is charged into the capacitor 5 is influenced. Since the first integration period has been preset to the predetermined time, if the period is set to a value that is integer times as long as a presumed period of power noises or the like, a positive component and a negative component of the noises can be set off. Since the second integration period, however, changes in proportion to the input voltage Vi, the external noises cannot be set off. There is, consequently, a problem that a conversion error is caused by the external noises.
It is, therefore, an object of the invention to solve the problem of the conventional technique and provide a dual-slope conversion type ADC which is hardly influenced by external noises.
According to the first aspect of the invention, the above object is accomplished by an analog/digital converter (ADC) comprising: switching means for switching an analog voltage as a conversion target and a reference voltage whose polarity is different from that of the analog voltage and sequentially outputting them; integrating means for continuously integrating the analog voltage and the reference voltage which are outputted from the switching means and forming an integration voltage; first comparing means for comparing the integration voltage with a base voltage and outputting a first comparison result; second comparing means for comparing the integration voltage with a voltage that is higher than the base voltage by a predetermined voltage and outputting a second comparison result; third comparing means for comparing the integration voltage with a voltage that is lower than the base voltage by a predetermined voltage and outputting a third comparison result; counting means for counting a time which is required from a start of the integration of the reference voltage in the integrating means to a timing when the first comparison result is inverted and outputting a count result as a digital signal corresponding to the analog voltage; first measuring means for measuring a difference between the inversion time of the first comparison result and that of the second comparison result; second measuring means for measuring a difference between the inversion time of the first comparison result and that of the third comparison result; and comparing means for comparing measurement results of the first and second measuring means and discriminating whether a difference between them lies within the permission value or not.
According to the first aspect of the invention, since the ADC is constructed as mentioned above, the following operation is executed.
First, the analog voltage as a conversion target is outputted from the switching means and integrated by the integrating means. Subsequently, the reference voltage is outputted from the switching means and continuously integrated by the integrating means. The integration voltage formed by the integrating means is compared with the base voltage by the first comparing means and the first comparison result is outputted. The time which is required from the start of the integration of the reference voltage by the integrating means to the inversion of the first comparison result is counted by the counting means. The count result is outputted as a digital signal.
The integration voltage is compared with the voltage that is higher than the base voltage by the predetermined voltage by the second comparing means and the second comparison result is outputted. The integration voltage is compared with the voltage that is lower than the base voltage by the predetermined voltage by the third comparing means and the third comparison result is outputted. The difference between the inversion time of the first comparison result and that of the second comparison result is measured by the first measuring means. The difference between the inversion time of the first comparison result and that of the third comparison result is measured by the second measuring means. The measurement results of the first and second measuring means are compared by the comparing means and whether a difference between them lies within the permission value or not is discriminated.
According to the second aspect of the invention, there is provided an ADC comprising: the switching means, integrating means, first, second, and third comparing means, and counting means which are similar to those in the first aspect of the invention; and external control means for generating a control signal for stopping the operation to an external circuit serving as a noise generation source for a period of time from a timing when the second or third comparison result has been inverted to a timing when the first comparison result is inverted.
According to the second aspect of the invention, the following operation is executed. First, an analog voltage as a conversion target is outputted from the switching means and integrated by the integrating means. Subsequently, the reference voltage is outputted from the switching means and continuously integrated by the integrating means. The integration voltage formed by the integrating means is compared with the base voltage by the first comparing means and a first comparison result is outputted. The time which is required from the start of the integration of the reference voltage by the integrating means to a timing when the first comparison result is inverted is counted by the counting means. A count result is outputted as a digital signal.
The integration voltage is compared with the voltage that is higher than the base voltage by a predetermined voltage by the second comparing means and the second comparison result is outputted. The integration voltage is compared with the voltage that is lower than the base voltage by a predetermined voltage by the third comparing means and the third comparison result is outputted. The second and third comparison results are supplied to the external control means. For a period of time from a timing when the second or third comparison result has been inverted to a timing when the first comparison result is inverted, the control signal to stop the operation of the external circuit serving as a noise generation source is generated.
The above and other objects and features of the present invention will become apparent from the following detailed description and the appended claims with reference to the accompanying drawings.